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lt c3892/ lt c3892 -1 / lt c3892 -2 1 38921fb for more information www.linear.com/ltc3892 typical application features description 60v low i q , dual, 2-phase synchronous step-down dc/dc controller the lt c ? 3892/ltc3892-1/ltc3892-2 is a high perfor - mance dual step-down dc / dc switching regulator control - ler that drives all n-channel synchronous power mosfet stages . power loss and noise are minimized by operating the two controller output stages out-of-phase. the gate drive voltage can be programmed from 5v to 10v to allow the use of logic or standard-level fets and to maximize efficiency . internal switches in the top gate drivers eliminate the need for external bootstrap diodes.a wide 4. 5v to 60v input supply range encompasses a wide range of intermediate bus voltages and battery chemistries . output voltages up to 99 % of v in can be regulated . opti- loop ? compensation allows the transient response and loop stability to be optimized over a wide range of output capacitance and esr values. the 29 a no-load quiescent current extends operating run time in battery powered systems . for a comparision of the ltc3892 to the ltc3892 -1 and ltc3892-2, see table 1 in the pin functions section of this data sheet. high efficiency dual 5v/12v output step-down converter n wide v in range: 4.5v to 60v (65v abs max) n wide output voltage range : 0. 8v v out 99 % ? v in n adjustable gate drive level 5v to 10v (opti-drive) n no external bootstrap diodes required n low operating i q : 29a (one channel on) n selectable gate drive uvlo thresholds n out-of-phase operation reduces required input capacitance and power supply induced noise n phase-lockable frequency: 75khz to 850khz n selectable continuous, pulse skipping or low ripple burst mode ? operation at light loads n selectable current limit (ltc3892/ltc3892-2) n very low dropout operation: 99% duty cycle n power good output voltage monitors ( lt c3892 / lt c3892 -2 ) n low shutdown i q : 3.6a n small 32-lead 5mm 5mm qfn package (ltc3892/ lt c3892 -2 ) or tssop package ( lt c3892 -1 ) l , lt , lt c , lt m , burst mode, opti-loop, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6144194, 6177787, 6580258. 4.7f 0.1f 15h 8m 100pf 100k 7.15k 34.8k 1nf 150f 1nf 0.1f 0.1f 5.6h 5m 7.5k 47f 100pf 0.1f 2.2nf 0.1f 220f 1nf ltc3892 vin run2 intv cc gnd sw2 bg2 tg2 boost2 sense2 + v fb2 ith2 track/ss2 12v sense2 C drvuv drv cc run1 sw1 bg1 tg1 boost1 sense1 + v fb1 ith1 track/ss1 sense1 C drvset vprg1 v out2 5a vin 12.5v to 60v 5v v out1 8a 3892 ta01 applications n automotive and industrial power systems n distributed dc power systems n high voltage battery operated systems v in = 12v v out = 5v burst mode operation gate drive drv cc =5v drv cc =6v drv cc =8v drv cc =10v load current (a) 0.01 0.1 1 10 88 89 90 91 92 93 94 95 96 efficiency (%) ef?ciency vs output current 3892 f01b efficiency vs output current downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 2 38921fb for more information www.linear.com/ltc3892 absolute maximum ratings input supply voltage (v in ) ......................... C0. 3v to 65v top side driver voltages (b oost1, boost2) ............................... C0. 3v to 76v switch voltage ( sw1 , sw2) .......................... C 5v to 70v drv cc , (boost1-sw1 ), (boost2-sw2) ....................................... C0. 3v to 11v b g1 , b g2 , t g1 , t g2 ........................................... ( note 8 ) ru n1 , ru n2 voltages ................................ C0. 3v to 65v sen se1 + , sen se2 + , sen se1 C sen se2 C voltages ................................. C0. 3v to 65v pllin / mode , freq voltages ...................... C0. 3v to 6v extv cc voltage ......................................... C0. 3v to 14v i t h1 , i t h2 , v fb1 , v fb2 voltages ..................... C0. 3v to 6v drvset , drvuv voltages ........................... C0. 3v to 6v (notes 1, 3) pin configuration track /s s1 , track /s s2 voltages .............. C0. 3v to 6v pgoo d1 , pgoo d2 voltages ( lt c3 892 / lt c3 892 -2 ) ............................. C0. 3v to 6v vpr g1 , ilim voltages ( lt c3 892 / lt c3 892 -2 ) ............................. C0. 3v to 6v operating junction temperature range ( note 2 ) lt c3 892 e , lt c3892 i, lt c3892 e -1 , lt c3892 i-1 , lt c3892 e -2 , lt c3892 i-2 ................... C 40 c to 125c lt c3892 h , lt c3892 h -1 , lt c3892 h-2 ................. C 40 c to 150c lt c3892 mp , lt c3892 mp-1 , lt c3892 m p-2 .................................... C 55 c to 150c storage temperature range .................. C 65 c to 150c ltc3892/ltc3892-2 ltc3892-1 32 33 gnd 31 30 29 28 27 26 25 9 10 11 12 top view uh package 32-lead (5mm 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 freq pllin/mode pgood1pgood2 intv cc run1run2 ilim boost1 bg1v in extv cc drv cc bg2 boost2 sw2 sense1 ? sense1 + v fb1 ith1vprg1 track/ss1 tg1 sw1 sense2 ? sense2 + v fb2 ith2 drvuv drvset track/ss2 tg2 t jmax = 150c, ja = 44c/w exposed pad (pin 33) is gnd, must be connected to gnd 12 3 4 5 6 7 8 9 1011 12 13 14 top view fe package 28-lead plastic tssop 2827 26 25 24 23 22 21 20 19 18 17 16 15 ith1 v fb1 sense1 + sense1 ? freq pllin/mode intv cc run1run2 sense2 ? sense2 + v fb2 ith2 drvuv track/ss1 tg1sw1 boost1 bg1 v in extv cc drv cc bg2boost2 sw2 tg2 track/ss2 drvset 29 gnd t jmax = 150c, ja = 30c/w exposed pad (pin 29) is gnd, must be connected to gnd downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 3 38921fb for more information www.linear.com/ltc3892 order information lead free finish tape and reel part marking* package description temperature range ltc3892euh#pbf ltc3892euh#trpbf 3892 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc3892iuh#pbf ltc3892iuh#trpbf 3892 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc3892huh#pbf ltc3892huh#trpbf 3892 32-lead (5mm 5mm) plastic qfn C40c to 150c ltc3892mpuh#pbf ltc3892mpuh#trpbf 3892 32-lead (5mm 5mm) plastic qfn C55c to 150c ltc3892efe-1#pbf ltc3892efe-1#trpbf ltc3892fe-1 28-lead plastic tssop C40c to 125c ltc3892ife-1#pbf ltc3892ife-1#trpbf ltc3892fe-1 28-lead plastic tssop C40c to 125c ltc3892hfe-1#pbf ltc3892hfe-1#trpbf ltc3892fe-1 28-lead plastic tssop C40c to 150c ltc3892mpfe-1#pbf ltc3892mpfe-1#trpbf ltc3892fe-1 28-lead plastic tssop C55c to 150c ltc3892euh-2#pbf ltc3892euh-2#trpbf 3892-2 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc3892iuh-2#pbf ltc3892iuh-2#trpbf 3892-2 32-lead (5mm 5mm) plastic qfn C40c to 125c ltc3892huh-2#pbf ltc3892huh-2#trpbf 3892-2 32-lead (5mm 5mm) plastic qfn C40c to 150c ltc3892mpuh-2#pbf ltc3892mpuh-2#trpbf 3892-2 32-lead (5mm 5mm) plastic qfn C55c to 150c consult ltc marketing for parts specified with wider operating temperature ranges . * the temperature grade is identified by a label on the shipping container . for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ . some packages are available in 500 unit reels through designated sales channels with #trmpbf suffix. http:// www .linear.com/product/ltc3892#orderinfo downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 4 38921fb for more information www.linear.com/ltc3892 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run1,2 = 5v, v extvcc = 0v, v drvset = 0v, vprg1 = float unless otherwise noted. symbol parameter conditions min typ max units v in input supply operating voltage range 4.5 60 v v fb1 channel 1 regulated feedback voltage (note 4) ith1 voltage = 1.2v 0 c to 85 c, vpr g1 = float ( ltc3892 / ltc3892-2 ) or ltc3892-1 vprg1 = float (ltc3892/ltc3892-2) or ltc3892-1 vprg1 = 0v (ltc3892/ltc3892-2) vprg1 = intv cc (ltc3892/ltc3892-2) l l l 0.792 0.788 3.234 4.890 0.800 0.800 3.3 5.0 0.808 0.812 3.366 5.110 v v v v v fb2 channel 2 regulated feedback voltage (note 4) ith2 voltage = 1.2v 0 c to 85 c l 0.792 0.788 0.800 0.800 0.808 0.812 v v i fb2 channel 2 feedback current (note 4) C2 50 na i fb1 channel 1 feedback current (note 4) vprg1 = float (ltc3892/ltc3892-2) or ltc3892-1 vprg1 = 0v (ltc3892/ltc3892-2) vprg1 = intv cc (ltc3892/ltc3892-2) C0.002 4 4 0.05 6 6 a a a v reflnreg reference voltage line regulation (note 4) v in = 4.5v to 60v 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop, ? ith voltage = 1.2v to 0.7v l 0.01 0.1 % (note 4) measured in servo loop, ? ith voltage = 1.2v to 2v l C0.01 C0.1 % g m1,2 transconductance amplifier g m (note 4) ith1,2 = 1.2v, sink/source 5a 2 mmho i q input dc supply current (note 5) v drvset = 0v pulse-skipping or forced continuous mode (one channel on) run1 = 5v and run2 = 0v or run2 = 5v and run1 = 0v, v fb1,2 = 0.83v (no load) 1.6 ma pulse-skipping or forced continuous mode (both channels on) run1,2 = 5v, v fb1,2 = 0.83v (no load) 2.8 ma sleep mode (one channel on) run1 = 5v and run2 = 0v or run2 = 5v and run1 = 0v, v fb1,2 = 0.83v (no load) l 29 55 a sleep mode (both channels on) run1,2 = 5v, v fb1,2 = 0.83v (no load) 34 55 a shutdown run1,2 = 0v 3.6 10 a uvlo undervoltage lockout drv cc ramping up drvuv = 0v drvuv = intv cc l l 4.0 7.5 4.2 7.8 v v drv cc ramping down drvuv = 0v drvuv = intv cc l l 3.6 6.4 3.8 6.7 4.0 7.0 v v v ovl1,2 feedback overvoltage protection measured at v fb1,2 relative to regulated v fb1,2 (ltc3892/ltc3892-1) 7 10 13 % i sense1,2 + sense + pin current 1 a i sense1,2 C sense C pins current v out1,2 < v intvcc C 0.5v v out1,2 > v intvcc + 0.5v 700 1 a a df max(tg) maximum duty factor for tg in dropout, freq = 0v 97.5 99 % i track/ss1,2 soft-start charge current v track/ss1,2 = 0v 8 10 12 a downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 5 38921fb for more information www.linear.com/ltc3892 electrical characteristics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run1,2 = 5v, v extvcc = 0v, v drvset = 0v, vprg1 = float unless otherwise noted. symbol parameter conditions min typ max units v run1,2 on run pin on threshold v run1 , v run2 rising l 1.22 1.275 1.33 v v run1,2 hyst run pin hysteresis 75 mv v sense(max) maximum current sense threshold v fb1,2 = 0.7v, v sense1,2 C = 3.3v i lim = float (ltc3892/ltc3892-2) or ltc3892-1 i lim = 0v (ltc3892/ltc3892-2) i lim = intv cc (ltc3892/ltc3892-2) l l l 66 43 90 75 50 100 84 58 109 mv mv mv v sense ( match ) matching between v sense1(max) and v sense2(max) v fb1,2 = 0.7v, v sense1,2 C = 3.3v i lim = float (ltc3892/ltc3892-2) or ltc3892-1 i lim = 0v (ltc3892/ltc3892-2) i lim = intv cc (ltc3892/ltc3892-2) l l l C8 C8 C8 0 0 0 8 8 8 mv mv mv gate drivertg1,2 pull-up on-resistance pull-down on-resistance v drvset = intv cc 2.2 1.0 bg1,2 pull-up on-resistance pull-down on-resistance v drvset = intv cc 2.2 1.0 bdsw1,2 boost to drv cc switch on- resistance v sw = 0v, v drvset = intv cc 3.7 tg1,2 t r tg1,2 t f tg transition time: rise time fall time (note 6) v drvset = intv cc c load = 3300pf c load = 3300pf 25 15 ns ns bg1,2 t r bg1,2 t f bg transition time: rise time fall time (note 6) v drvset = intv cc c load = 3300pf c load = 3300pf 25 15 ns ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver, v drvset = intv cc 55 ns bg/tg t 1d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver, v drvset = intv cc 50 ns t on(min)1,2 tg minimum on-time (note 7) v drvset = intv cc 80 ns drv cc linear regulator v drvcc(int) drv cc voltage from internal v in ldo v extvcc = 0v 7v < v in < 60v, drvset = 0v 11v < v in < 60v, drvset = intv cc 5.8 9.6 6.0 10.0 6.2 10.4 v v v ldoreg(int) drv cc load regulation from v in ldo i cc = 0ma to 50ma, v extvcc = 0v 0.9 2.0 % v drvcc(ext) drv cc voltage from internal extv cc ldo 7v < v extvcc < 13v, drvset = 0v 11v < v extvcc < 13v, drvset = intv cc 5.8 9.6 6.0 10.0 6.2 10.4 v v v ldoreg(ext) drv cc load regulation from internal extv cc ldo i cc = 0ma to 50ma, v extvcc = 8.5v, v drvset = 0v 0.7 2.0 % v extvcc extv cc ldo switchover voltage extv cc ramping positive drvuv = 0v drvuv = intv cc 4.5 7.4 4.7 7.7 4.9 8.0 v v v ldohys extv cc hysteresis 250 mv v drvcc(50k) programmable drv cc r drvset = 50k, v extvcc = 0v 5.0 v v drvcc(70k) programmable drv cc r drvset = 70k, v extvcc = 0v 6.4 7.0 7.6 v v drvcc(90k) programmable drv cc r drvset = 90k, v extvcc = 0v 9.0 v downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 6 38921fb for more information www.linear.com/ltc3892 the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 12v, v run1,2,3 = 5v, v extvcc = 0v, v drvset = 0v, vprg1 = float unless otherwise noted. electrical characteristics symbol parameter conditions min typ max units oscillator and phase-locked loopf 25k programmable frequency r freq =25k, pllin/mode = dc voltage 105 khz f 65k programmable frequency r freq = 65k, pllin/mode = dc voltage 375 440 505 khz f 105k programmable frequency r freq = 105k, pllin/mode = dc voltage 835 khz f low low fixed frequency v freq = 0v, pllin/mode = dc voltage 320 350 380 khz f high high fixed frequency v freq = intv cc , pllin/mode = dc voltage 485 535 585 khz f sync synchronizable frequency pllin/mode = external clock l 75 850 khz pllin v ih pllin v il pllin/mode input high level pllin/mode input low level pllin/mode = external clock pllin/mode = external clock l l 2.5 0.5 v v pgood1 and pgood2 outputs (ltc3892/ltc3892-2) v pgl pgood voltage low i pgood = 2ma 0.2 0.4 v i pgood pgood leakage current v pgood = 5v 1 a v pg pgood trip level v fb with respect to set regulated voltage v fb ramping negative hysteresis C13 C10 2.5 C7 % % v fb with respect to set regulated voltage v fb ramping positive hysteresis 7 10 2.5 13 % % t pg delay for reporting a fault 35 s note 1 : stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device . exposure to any absolute maximum ratings for extended periods may affect device reliability and lifetime . note 2: the ltc3892/ltc3892-1/ltc3892-2 is tested under pulsed load conditions such that t j t a . the ltc3892e/ltc3892e-1/ltc3892e-2 is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3892i/ltc3892i-1/ltc3892i-2 is guaranteed over the C40c to 125c operating junction temperature range, the ltc3892h/ltc3892h-1/ltc3892h-2 is guaranteed over the C40c to 150c operating junction temperature range, and the ltc3892mp/ltc3892mp-1/ltc3892mp-2 is tested and guaranteed over the C55c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than125c. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. the junction temperature (t j , in c) is calculated from the ambient temperature (t a , in c) and power dissipation (p d , in watts) according to the formula: t j = t a + (p d ? ja ) where ja = 44c/w for the qfn package and where ja = 30c/w for the tssop package. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. the maximum rated junction temperature will be exceeded when this protection is active. continuous operation above the specified absolute maximum operating junction temperature may impair device reliability or permanently damage the device. note 4: the ltc3892/ltc3892-1/ltc3892-2 is tested in a feedback loop that servos v ith1,2 to a specified voltage and measures the resultant v fb1,2 . the specification at 85c is not tested in production and is assured by design, characterization and correlation to production testing at other temperatures (125c for the ltc3892e/ltc3892e-1/ltc3892e-2 and ltc3892i/ltc3892i-1/ltc3892i-2, 150 c for the ltc3892h/ltc3892h-1/ ltc3892h-2 and ltc3892mp/ltc3892mp-1/ltc3892mp-2). for the ltc3892i/ltc3892i-1/ltc3892i-2 and ltc3892h/ltc3892h-1/ ltc3892h-2, the specification at 0c is not tested in production and is assured by design, characterization and correlation to production testing at C40c. for the ltc3892mp/ltc3892mp-1/ltc3892mp-2, the specification at 0c is not tested in production and is assured by design, characterization and correlation to production testing at C55c. note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information.note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levelsnote 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current >40% of i max (see minimum on-time considerations in the applications information section)note 8 : do not apply a voltage or current source to these pins . they must be connected to capacitive loads only , otherwise permanent damage may occur . downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 7 38921fb for more information www.linear.com/ltc3892 typical performance characteristics load step burst mode operation load step pulse-skipping mode load step forced continuous mode load current (a) 0.0001 0.001 0.01 0.1 1 10 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1k 10k efficiency (%) power loss (mw) vs load current ef?ciency and power loss 3892 g01 v out = 5v burst efficiency fcm loss burst loss pulse-skipping efficiency fcm efficiency pulse- skipping loss v in = 12v figure 11 circuit load current (a) 0.0001 0.001 0.01 0.1 1 10 0 10 20 30 40 50 60 70 80 90 100 efficiency (%) ef?ciency vs output current 3892 g02 v in = 10v v in = 20v v in = 30v v in = 40v v in = 50v v in = 60v figure 11 circuit v out = 5v burst mode operation input voltage (v) 0 5 10 15 20 25 30 35 40 45 50 55 60 86 87 88 89 90 91 92 93 94 95 96 efficiency (%) ef?ciency vs input voltage 3892 g03 figure 11 circuit v out = 5v i load =8a drvset=intv cc drvset=0v 50s/div v out 100mv/div ac coupled i l 2a/div 3892 g04 v in = 12v v out = 5v figure 13 circuit 50s/div v out 100mv/div ac coupled i l 2a/div 3892 g05 v in = 12v v out = 5v figure 13 circuit 50s/div v out 100mv/div ac coupled i l 2a/div 3892 g06 v in = 12v v out = 5v figure 13 circuit downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 8 38921fb for more information www.linear.com/ltc3892 drv cc and extv cc vs load current extv cc switchover and drv cc voltages vs temperature undervoltage lockout threshold vs temperature load current (ma) 0 drv cc voltage (v) 6.45.6 4.8 6 5.24.4 6.25.4 4.6 5.8 5 4.2 4 150 75 25 125 50 100 3892 g10 extv cc = 0v extv cc = 8.5v v bias = 12v drvset = gnd extv cc = 5v temperature (c) C75 drv cc voltage (v) 1110 87 5 96 4 3892 g11 150 125 25 0 C50 75 100 C25 50 drv cc (drvset = intv cc ) extv cc rising extv cc falling extv cc rising extv cc falling drv cc (drvset = 0v) drvuv = intv cc drvuv = gnd temperature (c) C75 drv cc voltage (v) 8 7.55.5 4.5 6.53.5 3 75 64 3892 g12 150 125 25 0 C50 75 100 C25 50 rising falling rising falling drvuv = intv cc drvuv = gnd typical performance characteristics inductor current at light load soft start-up regulated feedback voltage vs temperature 2s/div forced continuous mode burst mode operation 1a/div pulse skipping mode 3892 g07 v in = 12v v out = 5v i load = 1ma figure 13 circuit 2ms/div run1, 25v/div v out2 2v/divv out1 2v/div 3892 g08 figure 13 circuit temperature (c) -75 regulated feedback voltage (mv) 808806 802 800 796 804798 794 792 3892 g09 150 50 0 -50 100 125 25 -25 75 downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 9 38921fb for more information www.linear.com/ltc3892 typical performance characteristics sense pins total input current vs v sense voltage sense ? pin input bias current vs temperature foldback current limit maximum current sense threshold vs duty cycle maximum current sense threshold vs i th voltage shutdown (run) threshold vs temperature v sense common mode voltage (v) 0 sense current (a) 800700 300 100 500 0 600200 400 3892 g13 65 60 25 15 5 45 55 10 35 20 40 50 30 temperature (c) C75 sense current (a) 900500 300 700100 0 800400 600200 3892 g14 150 125 25 0 C50 75 100 C25 50 v out > intv cc + 0.5v v out < intv cc C 0.5v feedback voltage (mv) 0 maximum current sense voltage (mv) 120100 110 9050 30 7010 0 8040 6020 3892 g15 800 400 300 100 600 700 200 500 i lim = intv cc i lim = float i lim = gnd ltc3892-2 ltc3892/ltc3892-1 duty cycle (%) 0 maximum current sense voltage (mv) 100 9050 30 7010 0 8040 6020 3892 g16 100 40 30 10 60 90 80 70 20 50 i lim = intv cc i lim = float i lim = gnd v ith (v) 0 current sense voltage (mv) 100 0 C20C40 8040 6020 3892 g17 1.4 0.2 0.6 1.2 1 0.8 0.4 i lim = gnd i lim = float i lim = i ntv cc burst mode operation 5% duty cycle pulse-skipping forced continuous mode temperature (c) C75 run pin voltage (v) 1.4 1.251.15 1.351.05 1 1.2 1.31.1 3892 g18 150 125 25 0 C50 75 100 C25 50 rising falling downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 10 38921fb for more information www.linear.com/ltc3892 typical performance characteristics oscillator frequency vs temperature track/ss pull-up current vs temperature drv cc line regulation shutdown current vs temperature shutdown current vs input voltage quiescent current vs temperature input voltage (v) 0 drv cc voltage (v) 1110 6 85 97 3892 g19 65 60 25 15 5 45 55 10 35 20 40 50 30 drvset = intv cc drvset = gnd temperature (c) C75 shutdown current (a) 84 70 2 63 1 5 3892 g20 150 125 25 0 C50 75 100 C25 50 v in = 12v input voltage (v) 0 shutdown current (a) 1410 6 80 12 42 3892 g21 70 60 10 20 40 50 30 temperature (c) C75 C50 C25 0 25 50 75 100 125 150 0 10 20 30 40 50 60 70 80 quiescent current (a) 3899 g22 v in =12v one channel on burst mode operation dr vset = 70k? drvset=intv cc drvset=gnd temperature (c) -75 frequency (khz) 600500 550450 350 400300 -25 25 -50 0 75 100 3892 g23 150 50 125 freq = intv cc freq = gnd temperature (c) C75 track /ss current (a) 1210 11.5 8 9 11 9.58.5 10.5 3892 g24 150 125 25 0 C50 75 100 C25 50 downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 11 38921fb for more information www.linear.com/ltc3892 pin functions (qfn (ltc3892 and ltc3892-2)/tssop (ltc3892-1)) freq ( pin 1 / pin 5 ): the frequency control pin for the internal vco . connecting this pin to gnd forces the vco to a fixed low frequency of 350khz. connecting this pin to intv cc forces the vco to a fixed high frequency of 535khz . other frequencies between 50khz and 900khz can be programmed using a resistor between freq and gnd . the resistor and an internal 20a source current create a voltage used by the internal oscillator to set the frequency . pllin / mode ( pin 2 / pin 6 ): external synchronization input to phase detector and forced continuous mode input . when an external clock is applied to this pin , the phase-locked loop will force the rising t g1 signal to be synchronized with the rising edge of the external clock , and the regulators will oper - ate in forced continuous mode on the ltc3892 / ltc3892-1 and in pulse-skipping mode on the ltc3892-2 . when not synchronizing to an external clock , this input , which acts on both controllers , determines how the ltc3892 / ltc3892-1 / ltc3892 -2 operates at light loads . pulling this pin to ground selects burst mode operation . an internal 100k resistor to ground also invokes burst mode operation when the pin is floated . tying this pin to intv cc forces continuous inductor current operation . tying this pin to a voltage greater than 1. 1v and less than intv cc C 1. 3v selects pulse-skipping operation . this can be done by connecting a 100k resistor from this pin to intv cc . pgood1, pgoo d2 ( pins 3 , 4 /na): open-drain logic output. pgoo d1, 2 is pulled to ground when the voltage on the respective v fb1,2 pin is not within 10% of its set point . these pins are available on the ltc3892 and ltc3892-2, but not on the ltc3892-1. intv cc ( pin 5 / pin 7 ): output of the internal 5v low drop - out regulator . the low voltage analog and digital circuits are powered from this voltage source . a low esr 0.1f ceramic bypass capacitor should be connected between intv cc and gnd , as close as possible to the ic . intv cc should not be used to power or bias any external circuitry other than to configure the freq , pllin /mode, drvset , drvuv and vprg1 pins. ru n1 , ru n2 ( pins 6 , 7 / pins 8 , 9 ): run control inputs for each controller . forcing any of these pins below 1. 2v shuts down that controller . forcing both of these pins below 0. 7v shuts down the entire lt c3892 / lt c3892 -1 / lt c3892 -2 , reducing quiescent current to approximately 3.6a. ilim ( pin 8 / na): current comparator sense voltage range input. tying this pin to gnd or intv cc or floating it sets the maximum current sense threshold ( for both channels ) to one of three different levels (50mv, 100mv, or 75mv respectively). this pin is available on the ltc3892 and ltc3892-2 , but not on the ltc3892-1 . for the ltc3892-1 , the maximum current sense threshold is 75mv.v fb2 ( pin 11 / pin 12 ): this pin receives the remotely sensed feedback voltage for channel 2 from an external resistor divider across the output. drvuv (pin13/ pin 14 ): determines the higher or lower drv cc uvlo and extv cc switchover thresholds , as listed on the electrical characteristics table . connecting drvuv to gnd chooses the lower thresholds whereas tying drvuv to intv cc chooses the higher thresholds. drvset ( pin 14 / pin 15 ): sets the regulated output volt - age of the drv cc ldo regulator . connecting this pin to gnd sets drv cc to 6v whereas connecting it to intv cc sets drv cc to 10v. voltages between 5v and 10v can be programmed by placing a resistor (50k to 100k) between the drvset pin and gnd. drv cc ( pin 20 / pin 21 ): output of the internal or external low dropout (ldo) regulator . the gate drivers are pow - ered from this voltage source . the drv cc voltage is set by the drvset pin . must be decoupled to ground with a minimum of 4.7f ceramic or other low esr capacitor . do not use the drv cc pin for any other purpose. extv cc ( pin 21 / pin 22 ): external power input to an internal ldo connected to drv cc . this ldo supplies drv cc power , bypassing the internal ldo powered from v in whenever extv cc is higher than its switchover threshold (4.7v or 7.7v depending on the drvset pin ). see extv cc con - nection in the applications information section . do not float or exceed 14v on this pin . do not connect extv cc to a voltage greater than v in . connect to gnd if not used . v in ( pin 22 / pin 23 ): main supply pin . a bypass capacitor should be tied between this pin and the gnd pin.bg1, b g2 ( pins 23 , 19 / pins 24 , 20 ): high current gate drives for bottom n-channel mosfets . voltage swing at these pins is from ground to drv cc . downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 12 38921fb for more information www.linear.com/ltc3892 pin functions (qfn (ltc3892 and ltc3892-2)/tssop (ltc3892-1)) boost1 , boost2 ( pins 24 , 18 / pins 25 , 19 ): bootstrapped supplies to the topside floating drivers . capacitors are connected between the boost and sw pins . voltage swing at boost1 and boost2 pins is from approximately drv cc to (v in1,2 + drv cc ). sw1, sw2 ( pins 25 , 17 / pins 26 , 18 ): switch node con - nections to inductors. t g1, t g2 ( pins 26 , 16 / pins 27 , 17 ): high current gate drives for top n-channel mosfets . these are the outputs of floating drivers with a voltage swing equal to drv cc superimposed on the switch node voltage sw.track/ss1, track /ss2 ( pins 27 , 15 / pins 28 , 16 ): external tracking and soft-start input . the ltc3892/ ltc3892-1/ltc3892 -2 regulates the negative input (ea C ) of the error amplifier to the smaller of 0.8v or the voltage on the track / ss pin . an internal 10a pull-up current source is connected to this pin . a capacitor to ground at this pin sets the ramp time at start-up to the final regulated output voltage . alternatively , a resistor divider on another supply connected to the track / ss pin allows the ltc3892 / ltc3892-1/ltc3892 -2 output voltage to track the other supply during start-up . the track / ss pin is pulled low in shutdown or in undervoltage lockout. vprg1 ( pin 28 / na): channel 1 output voltage control pin . this pin sets channel 1 to adjustable output mode using external feedback resistors or fixed 3.3v/5v output mode . floating this pin allows the output to be programmed from 0.8v to 60v with an external resistor divider , regulating v fb1 to 0.8v. this pin is available on the ltc3892 and ltc3892-2, but not on the ltc3892-1.ith1, it h2 ( pins 29 , 12 / pins 1 , 13 ): error amplifier outputs and switching regulator compensation points . each associated channel s current comparator trip point increases with this control voltage.v fb1 ( pin 30 / pin 2 ): for the ltc3892-1, this pin receives the remotely sensed feedback voltage for channel 1 from an external resistor divider across the output. for the ltc3892 and ltc3892-2, if the vpr g1 pin is float - ing, the v fb1 pin receives the remotely sensed feedback voltage for channel ? 1 from an external resistor divider across the output . if vpr g1 is tied to gnd or intv cc , the v fb1 pin receives the remotely sensed output voltage directly.sense1 + , sen se2 + ( pins 31 , 10 / pins 3 , 11 ): the (+) input to the differential current comparators . the ith pin voltage and controlled offsets between the sense C and sense + pins in conjunction with r sense set the current trip threshold.sense1 ? , sen se2 ? ( pins 32 , 9 / pins 4 , 10 ): the (C) input to the differential current comparators . when sen se1 ,2 C is greater than intv cc , then sen se1,2 C pin supplies current to the current comparator. gnd ( exposed pad pin 33 / exposed pad pin 29 ): ground . the exposed pad must be soldered to the pcb for rated electrical and thermal performance. table 1. summary of the differences between the ltc3892, ltc3892-1 and ltc3892-2 ltc3892 ltc3892-1 ltc3892-2 ilim pin for selectable current sense voltage? yes ; 50mv, 75mv, or 100mv no; fixed 75mv yes ; 50mv, 75mv, or 100mv vprg1 pin for fixed or adjustable v out1 ? yes ; fixed 3.3v or 5v (with internal resistor divider) or adjustable with external resistor divider no; only adjustable with external resistor divider yes ; fixed 3.3v or 5v (with internal resistor divider) or adjustable with external resistor divider independent pgood output for each channel? yes ; pgood1 and pgood2 no pgood function yes ; pgood1 and pgood2 output overvoltage protection bottom gate "crowbar?" yes ; bg forced on yes ; bg forced on no; bg not forced on current foldback during overcurrent events ? yes yes no light load operation when synchronized to external clock using pllin/mode forced continuous forced continuous pulse-skipping (discontinuous) package 32-pin 5mm x 5mm qfn (uh32) 28-lead tssop (fe28) 32-pin 5mm x 5mm qfn (uh32) downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 13 38921fb for more information www.linear.com/ltc3892 functional diagrams boost1,2 drv cc tg1,2 top bot channels 1 and 2 s clk1 clk2 pfd sync det vco q r q bot shdn sleep 0.425v top on sw1,2 bg1,2 drv cc gnd sense1,2 + sense1,2 C ith1,2 track/ss1,2 shdn run1,2 shdn rst 2(v fb ) foldback 10a v fb1,2 r a r c r b c c 0.80vtrack/ss 0.88v ov c b c out v in1,2 v out1,2 r sense l switching logic dropout det +C +C +C C+ + i r 3mv i cmp 2.8v 0.65v slope comp + C + C c in +C r2 r1 c c2 c ss 38921 fd 150na 3.5v 20a freq pllin/mode 100k intv cc ldo drv cc ldo/uvlo control 4.7v/ 7.7v en +C en 2.00v1.20v drvset extv cc drvuv v in drv cc 20a 4r r +C +C intv cc ea C pgood1 ea1 C 0.88v0.72v + C + C + C + C pgood2 ea2 C 0.88v0.72v current limit i lim vprg1 ltc3892 and ltc3892-2 not on ltc3892-1 vprg1 affects channel 1 only,v out2 is always adjustable (r1 = 0, r2 = ) ltc3892-1 (r1 = 0, r2 = ) vprg1 float gnd intv cc r1 0 625k 1.05m r2 200k200k v out1 adjustable 3.3v fixed 5v fixed ltc3892 and ltc3892-1 downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 14 38921fb for more information www.linear.com/ltc3892 operation (refer to the functional diagrams) main control loop the ltc3892 / ltc3892-1 / ltc3892 -2 uses a constant frequency, current mode step-down architecture . the two controller channels operate 180 out of phase with each other. during normal operation , the external top mosfet is turned on when the clock for that channel sets the rs latch, and is turned off when the main current compara - tor, i cmp , resets the rs latch . the peak inductor current at which i cmp trips and resets the latch is controlled by the voltage on the ith pin , which is the output of the er - ror amplifier , ea . the error amplifier compares the output voltage feedback signal at the v fb pin ( which is generated with an external resistor divider connected across the output voltage , v out , to ground ) to the internal 0.800v reference voltage . when the load current increases , it causes a slight decrease in v fb relative to the reference , which causes the ea to increase the ith voltage until the average inductor current matches the new load current. after the top mosfet is turned off each cycle , the bottom mosfet is turned on until either the inductor current starts to reverse , as indicated by the current comparator i r , or the beginning of the next clock cycle. drv cc /extv cc /intv cc power power for the top and bottom mosfet drivers is derived from the drv cc pin . the drv cc supply voltage can be pro - grammed from 5v to 10v through control of the drvset pin. when the extv cc pin is tied to a voltage below its switchover voltage (4. 7v or 7. 7v depending on the drvset voltage), the v in ldo ( low dropout linear regulator ) sup - plies power from v in to drv cc . if extv cc is taken above its switchover voltage , the v in ldo is turned off and an extv cc ldo is turned on . once enabled , the extv cc ldo supplies power from extv cc to drv cc . using the extv cc pin allows the drv cc power to be derived from a high efficiency external source such as one of the ltc3892/ ltc3892-1/ltc3892-2 switching regulator outputs.each top mosfet driver is biased from the floating boot - strap capacitor , c b , which normally recharges during each cycle through an internal switch whenever sw goes low . if the input voltage decreases to a voltage close to its output, the loop may enter dropout and attempt to turn on the top mosfet continuously . the dropout detector detects this and forces the top mosfet off for about one- twelfth of the clock period every tenth cycle to allow c b to recharge, resulting in about 99% duty cycle. the intv cc supply powers most of the other internal circuits in the ltc3892/ltc3892-1/ltc3892-2. the intv cc ldo regulates to a fixed value of 5v and its power is derived from the drv cc supply. shutdown and start-up (run, track/ss pins) the two channels of the ltc3892/ltc3892-1/ltc3892-2 can be independently shut down using the ru n1 and run2 pins . pulling a run pin below 1.2v shuts down the main control loop for that channel . pulling both pins below 0.7v disables both controllers and most internal circuits, including the drv cc and intv cc ldos . in this state, the ltc3892/ltc3892-1/ltc3892 -2 draws only 3.6a of quiescent current.releasing a run pin allows a small 150na internal current to pull up the pin to enable that controller . each run pin may be externally pulled up or driven directly by logic . each run pin can tolerate up to 65v ( absolute maximum ), so it can be conveniently tied to v in in always-on applications where one or both controllers are enabled continuously and never shut down. the start-up of each controller s output voltage v out is controlled by the voltage on the track / ss pin (track/ ss1 for channel 1 , track /ss2 for channel 2 ). when the voltage on the track / ss pin is less than the 0.8v internal reference, the ltc3892/ltc3892-1/ltc3892 -2 regulates the v fb voltage to the track / ss pin voltage instead of the 0.8v reference . this allows the track / ss pin to be used to program a soft-start by connecting an external capacitor from the track / ss pin to gnd . an internal 10 a pull-up current charges this capacitor creating a voltage ramp on the track / ss pin . as the track / ss voltage rises linearly from 0v to 0.8v ( and beyond up to about 4v), the output voltage v out rises smoothly from zero to its final value. downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 15 38921fb for more information www.linear.com/ltc3892 operation (refer to the functional diagrams) alternatively the track / ss pins can be used to make the start-up of v out to track that of another supply . typically , this requires connecting to the track / ss pin an external resistor divider from the other supply to ground (see applications information section).light load current operation (burst mode operation, pulse-skipping or forced continuous mode) (pllin/mode pin) the ltc3892/ltc3892-1/ltc3892 -2 can be enabled to enter high efficiency burst mode operation , pulse-skipping mode, or forced continuous conduction mode at low load currents. to select burst mode operation , tie the pllin / mode pin to gnd . to select forced continuous opera - tion, tie the pllin / mode pin to intv cc . to select pulse- skipping mode , tie the pllin / mode pin to a dc voltage greater than 1.1v and less than intv cc C 1.3v. this can be done by connecting a 100k resistor between pllin / mode and intv cc . when a controller is enabled for burst mode operation , the minimum peak current in the inductor is set to ap - proximately 25 % of the maximum sense voltage even when the voltage on the ith pin indicates a lower value . if the average inductor current is higher than the load cur - rent, the error amplifier, ea, will decrease the voltage on the ith pin . when the ith voltage drops below 0.425v, the internal sleep signal goes high ( enabling sleep mode ) and both external mosfets are turned off . the ith pin is then disconnected from the output of the ea and parked at 0.450v. in sleep mode , much of the internal circuitry is turned off, reducing the quiescent current that the ltc3892/ ltc3892-1/ltc3892 -2 draws . if one channel is in sleep mode and the other channel is shut down, the ltc3892/ltc3892-1/ltc3892 -2 draws only 29 a of quiescent current ( with drvset = 0v). if both channels are in sleep mode, it draws only 34 a of quiescent current . in sleep mode, the load current is supplied by the output capacitor . as the output voltage decreases , the ea s output begins to rise . when the output voltage drops enough , the ith pin is reconnected to the output of the ea , the sleep signal goes low , and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation , the inductor current is not allowed to reverse . the reverse current comparator (i r ) turns off the bottom external mosfet just before the inductor current reaches zero , preventing it from reversing and going negative . thus , the controller operates discontinuously. in forced continuous operation , the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the ith pin , just as in normal operation . in this mode , the efficiency at light loads is lower than in burst mode operation . however , continuous operation has the advantage of lower output voltage ripple and less interference to audio circuitry . in forced continuous mode , the output ripple is independent of load current. when the pllin / mode pin is connected for pulse-skipping mode, the ltc3892/ltc3892-1/ltc3892 -2 operates in pwm pulse-skipping mode at light loads . in this mode , constant frequency operation is maintained down to ap - proximately 1 % of designed maximum output current . at ver y light loads , the current comparator , i cmp , may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses ). the inductor current is not allowed to reverse ( discontinuous operation ). this mode , like forced continuous operation , exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation . it provides higher low current efficiency than forced continuous mode , but not nearly as high as burst mode operation.when an external clock is connected to the pllin /mode pin to synchronize the internal oscillator ( see the frequency selection and phase-locked loop section ), the ltc3892/ ltc3892 -1 operate in forced continuous mode while the ltc3892 -2 operates in discontinuous pulse skipping mode . downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 16 38921fb for more information www.linear.com/ltc3892 operation (refer to the functional diagrams) frequency selection and phase-locked loop (freq and pllin/mode pins) the selection of switching frequency is a trade-off between efficiency and component size . low frequency opera - tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and / or capacitance to maintain low output ripple voltage.the switching frequency of the ltc3892/ltc3892-1/ ltc3892-2 s controllers can be selected using the freq pin.if the pllin / mode pin is not being driven by an external clock source , the freq pin can be tied to gnd , tied to intv cc or programmed through an external resistor . tying freq to gnd selects 350khz while tying freq to intv cc selects 535khz. placing a resistor between freq and gnd allows the frequency to be programmed between 50khz and 900khz, as shown in figure 9.a phase-locked loop (pll) is available on the ltc3892/ ltc3892-1/ltc3892 -2 to synchronize the internal oscil - lator to an external clock source that is connected to the pllin/ mode pin . the ltc3892/ltc3892-1/ltc3892-2s phase detector adjusts the voltage ( through an internal lowpass filter ) of the vco input to align the turn-on of controller 1 s external top mosfet to the rising edge of the synchronizing signal . thus , the turn-on of controller 2 s external top mosfet is 180 out of phase to the rising edge of the external clock source. the vco input voltage is prebiased to the operating fre - quency set by the freq pin before the external clock is applied. if prebiased near the external clock frequency , the pll loop only needs to make slight changes to the vco input in order to synchronize the rising edge of the external clock s to the rising edge of t g1. the ability to prebias the loop filter allows the pll to lock-in rapidly without deviating far from the desired frequency. the typical capture range of the ltc3892/ltc3892-1/ ltc3892-2 s phase-locked loop is from approximately 55khz to 1mhz, with a guarantee to be between 75khz and 850khz. in other words , the ltc3892/ltc3892-1/ ltc3892-2 s pll is guaranteed to lock to an external clock source whose frequency is between 75khz and 850khz. the typical input clock thresholds on the pllin /mode pin are 1.6v (rising) and 1.1v (falling). it is recommended that the external clock source swing from ground (0v) to at least 2.5v.when an external clock is connected to the pllin /mode pin to synchronize the internal oscillator , the ltc3892/ ltc3892 -1 operate in forced continuous mode while the ltc3892 -2 operates in discontinuous pulse skipping mode . output overvoltage protection (ltc3892/ltc3892-1, not on ltc3892-2) each channel has an overvoltage comparator that guards against transient overshoots as well as other more seri - ous conditions that may overvoltage the output . when the v fb1,2 pin rises by more than 10 % above its regula - tion point of 0.800v, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. foldback current (ltc3892/ltc3892-1, not on ltc3892-2) when the output voltage falls to less than 70 % of its nominal level , foldback current limiting is activated , pro - gressively lowering the peak current limit in proportion to the severity of the overcurrent or short-cir cuit condition . foldback current limiting is disabled during the soft-start interval ( as long as the v fb1,2 voltage is keeping up with the track/ss1,2 voltage). current foldback limiting is intended to limit power dissipation during overcurrent and short-circuit fault conditions . note that while the current foldback func - tion does not exist on the ltc3892 -2 version , it is still inherently protected during these fault conditions . the ltc3892 / ltc3892-1 / ltc3892-2 s peak current mode control architecture constantly monitors the inductor current and prevents current runaway under all conditions . downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 17 38921fb for more information www.linear.com/ltc3892 applications information 38921 f03 to sense filter next to the controller inductor or r sense current flow c out figure 1. sense lines placement with inductor or sense resistor the typical application on the first page is a basic ltc3892 / ltc3892-1 / ltc3892 -2 application circuit . ltc3892/ltc3892-1/ltc3892 -2 can be configured to use either dcr ( inductor resistance ) sensing or low value resistor sensing . the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy . dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient , especially in high current applications . however , current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load requirement , and begins with the selection of r sense ( if r sense is used ) and inductor value . next , the power mosfets and schottky diodes are selected . finally , input and output capacitors are selected.sense + and sense ? pins the sense + and sense C pins are the inputs to the cur - rent comparators . the common mode voltage range on these pins is 0v to 65v ( absolute maximum ), enabling the ltc3892/ltc3892-1/ltc3892 -2 to regulate output voltages up to a nominal 60v ( allowing margin for toler - ances and transients ). the sense + pin is high impedance over the full common mode range , drawing at most 1a. this high impedance allows the current comparators to be used in inductor dcr sensing . the impedance of the sense C pin changes depending on the common mode voltage. when sense C is less than intv cc C 0.5v, a small current of less than 1 a flows out of the pin . when sense C is above intv cc + 0.5v, a higher current (700a) flows into the pin . between intv cc C 0.5v and intv cc + 0.5v, the current transitions from the smaller current to the higher current.filter components mutual to the sense lines should be placed close to the ltc3892/ltc3892-1/ltc3892-2, and the sense lines should run close together to a kelvin con - nection underneath the current sense element ( shown in figure 1 ). sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and making the programmed current limit unpredictable . if dcr sensing is used (figure 2b), resistor r1 should be placed close to the switching node , to prevent noise from coupling into sensitive small-signal nodes. low value resistor current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current.each controller s current comparator has a maximum threshold v sense(max) . for the ltc3892-1, v sense(max) is fixed at 75mv, while for the ltc3892 and ltc3892-2, v sense(max) is either 50mv, 75mv or 100mv, as deter - mined by the state of the ilim pin . the current comparator threshold voltage sets the peak of the inductor current , yielding a maximum average output current , i max , equal to the peak value less half the peak-to-peak ripple current , ? i l . to calculate the sense resistor value , use the equation : r sense = v sense(max) i max + ? i l 2 when using a controller in very low dropout conditions , the maximum output current level will be reduced due to the internal compensation required to meet stability criteria for buck regulators operating at greater than 50 % duty factor. a curve is provided in the typical performance characteristics section to estimate this reduction in peak inductor current depending upon the operating duty factor . inductor dcr sensingfor applications requiring the highest possible efficiency at high load currents , the ltc3892 / ltc3892-1 / ltc3892-2 is capable of sensing the voltage drop across the induc - tor dcr , as shown in figure ?2b . the dcr of the inductor represents the small amount of dc winding resistance of downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 18 38921fb for more information www.linear.com/ltc3892 38921 f04b ltc3892/ ltc3892-1/ ltc3892-2 v in1,2 v out1,2 c1* r2 *place c1 near sense pins r sense(eq) = dcr(r2/(r1+r2)) l dcr inductor r1 (r1||r2) ? c1 = l/dcr boost tg sw bg gnd sense1,2 C sense1,2 + the copper , which can be less than 1m for today s low value, high current inductors . in a high current application requiring such an inductor , power loss through a sense resistor would cost several points of efficiency compared to inductor dcr sensing. if the external (r1||r2) ? c1 time constant is chosen to be exactly equal to the l / dcr time constant , the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value . to properly dimension the external filter components , the dcr of the inductor must be known . it can be measured using a good rlc meter , but the dcr tolerance is not always the same and varies with temperature ; consult the manufacturers data sheets for detailed information.using the inductor ripple current value from the inductor value calculation section , the target sense resistor value is : r sense(equiv) = v sense(max) i max + ? i l 2 to ensure that the application will deliver full load current over the full operating temperature range , choose the minimum value for v sense(max) in the electrical charac - teristics table.next, determine the dcr of the inductor . when provided , use the manufacturer s maximum value , usually given at 20c. increase this value to account for the temperature coefficient of copper resistance , which is approximately 0.4%/c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value (r d ), use the divider ratio: r d = r sense(equiv) dcr max at t l(max) c1 is usually selected to be in the range of 0 .1 f to 0 .47f. this forces r1|| r2 to around 2k, reducing error that might have been caused by the sense + pins 1a current. the equivalent resistance r1||r2 is scaled to the room temperature inductance and maximum dcr: ? r1 ? r2 = l (dcr at 20 c) ? c1 the sense resistor values are: ? r1 = r1 ? r2 r d ; r2 = r1 ? r d 1 ? r d the maximum power loss in r1 is related to duty cycle , and will occur in continuous mode at the maximum input voltage: p loss r1 = v in(max) ? v out ( ) ? v out r1 applications information 38921 f04a ltc3892/ ltc3892-1/ ltc3892-2 boost tg sw bg gnd sense1,2 C sense1,2 + v in1,2 v out1,2 r sense capplaced near sense pins (2b) using the inductor dcr to sense current (2a) using a resistor to sense current figure 2. current sensing methods downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 19 38921fb for more information www.linear.com/ltc3892 ensure that r1 has a power rating higher than this value . if high efficiency is necessary at light loads , consider this power loss when deciding whether to use dcr sensing or sense resistors . light load power loss can be modestly higher with a dcr network than with a sense resistor , due to the extra switching losses incurred through r1. however , dcr sensing eliminates a sense resistor , reduces conduction losses and provides higher efficiency at heavy loads . peak efficiency is about the same with either method . inductor value calculation the operating frequency and inductor selection are inter - related in that higher operating frequencies allow the use of smaller inductor and capacitor values . so why would anyone ever choose to operate at lower frequencies with larger components ? the answer is efficiency . a higher frequency generally results in lower efficiency because of mosfet switching and gate charge losses . in addition to this basic trade-off, the effect of inductor value on ripple current and low current operation must also be considered . the inductor value has a direct effect on ripple current . the inductor ripple current , ? i l , decreases with higher induc - tance or higher frequency and increases with higher v in : ? i l = 1 f ( ) l ( ) v out 1 ? v out v in ?? ? ?? ? accepting larger values of ? i l allows the use of low inductances, but results in higher output voltage ripple and greater core losses . a reasonable starting point for setting ripple current is ? i l = 0 .3(i max ). the maximum ? i l occurs at the maximum input voltage. the inductor value also has secondary effects . the tran - sition to burst mode operation begins when the average inductor current required results in a peak current below 25% of the current limit determined by r sense . lower inductor values (higher ? i l ) will cause this to occur at lower load currents , which can cause a dip in efficiency in the upper range of low current operation . in burst mode operation, lower inductance values will cause the burst frequency to decrease. inductor core selectiononce the value for l is known, the type of inductor must be selected . core loss is independent of core size for a fixed inductor value , but it is very dependent on inductance value selected . as inductance increases , core losses go down. unfortunately , increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred for high switching frequencies , so design goals can con - centrate on copper loss and preventing saturation . ferrite core material saturates hard , which means that induc - tance collapses abruptly when the peak design current is exceeded . this results in an abrupt increase in inductor ripple current and consequent output voltage ripple . do not allow the core to saturate!power mosfet and schottky diode (optional) selectiont wo external power mosfet s must be selected for each controller in the ltc3892/ltc3892-1/ltc3892-2: one n-channel mosfet for the top (main) switch and one n-channel mosfet for the bottom (synchronous) switch . the peak-to-peak drive levels are set by the drv cc volt - age. this voltage can range from 5v to 10v depending on configuration of the drvset pin . therefore , both logic-level and standard-level threshold mosfets can be used in most applications depending on the programmed drv cc voltage . different uvlo thresholds appropriate for logic-level or standard-level threshold mosfets can be selected by the drvuv pin . pay close attention to the bv dss specification for the mosfets as well. the ltc3892/ltc3892-1/ltc3892-2 s unique ability to adjust the gate drive level between 5v to 10v ( opti-drive ) allows an application circuit to be precisely optimized for efficiency . when adjusting the gate drive level , the final arbiter is the total input current for the regulator . if a change is made and the input current decreases , then the efficiency has improved . if there is no change in input current, then there is no change in efficiency. selection criteria for the power mosfets include the on-resistance r ds(on) , miller capacitance c miller , input applications information downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 20 38921fb for more information www.linear.com/ltc3892 applications information voltage and maximum output current . miller capacitance , c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately flat divided by the specified change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specified v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle = v out v in synchronous switch duty cycle = v in ? v out v in the mosfet power dissipations at maximum output current are given by: p main = v out v in i out(max) ( ) 2 1 + ( ) r ds(on) + (v in ) 2 i out(max) 2 ?? ? ?? ? (r dr )(c miller ) ? 1 v drvcc ? v thmin + 1 v thmin ?? ? ?? ? (f) p sync = v in ? v out v in i out(max) ( ) 2 1 + ( ) r ds(on) where is the temperature dependency of r ds(on) and r dr (approximately 2) is the effective driver resistance at the mosfet s miller threshold voltage . v thmin is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the main n-channel equations include an additional term for transition losses , which are highest at high input voltages . for v in < 20v the high current efficiency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency . the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve , but = 0 .005/ c can be used as an approximation for low voltage mosfets. optional schottky diodes placed across the synchronous mosfet conduct during the dead-time between the con - duction of the two power mosfets . this prevents the body diode of the synchronous mosfet from turning on, storing charge during the dead-time and requiring a reverse recovery period that could cost as much as 3 % in efficiency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current . larger diodes result in additional transition losses due to their larger junction capacitance. c in and c out selection the selection of c in is simplified by the 2- phase architec - ture and its impact on the worst-case rms current drawn through the input network ( batter y / fuse / capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating . the controller with the highest (v out )(i out ) product needs to be used in the formula shown in equation 1 to determine the maximum rms capacitor current requirement . increasing the out - put current drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the opt-of-phase technique typically reduces the input capacitor s rms ripple current by a factor of 30 % to 70 % when compared to a single phase power supply solution. in continuous mode , the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients , a low esr capacitor sized for the maximum rms current of one channel must be used . the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in ? v out ( ) ?? ?? 1/2 (1) downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 21 38921fb for more information www.linear.com/ltc3892 applications information this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief . note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life . this makes it advisable to further derate the capacitor , or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design . due to the high operating frequency of the ltc3892/ltc3892-1/ ltc3892-2, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question . the benefit of the ltc3892 / ltc3892-1 / ltc3892 -2 2- phase operation can be calculated by using equation 1 for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time . the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitor s esr . this is why the input capacitor s requirement calculated above for the worst-case controller is adequate for the dual controller design . also , the input protection fuse resistance , battery resistance , and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2- phase system . the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply /battery is included in the efficiency testing . the drains of the top mosfets should be placed within 1cm of each other and share a common c in (s). separating the drains and c in may produce undesirable voltage and current resonances at v in . a small (0.1 f to 1 f) bypass capacitor between the chip v bias pin and ground , placed close to the ltc3892/ ltc3892-1/ltc3892-2, is also suggested . a 2.2 to 10 resistor placed between c in (c1) and the v bias pin provides further isolation, but is not required.the selection of c out is driven by the effective series resistance (esr). typically , once the esr requirement is satisfied , the capacitance is adequate for filtering . the output ripple ( ? v out ) is approximated by: ? v out ? i l esr + 1 8 ? f ? c out ?? ? ?? ? where f is the operating frequency , c out is the output capacitance and ? i l is the ripple current in the inductor . the output ripple is highest at maximum input voltage since ? i l increases with input voltage. setting output voltage the ltc3892/ltc3892-1/ltc3892 -2 output voltages are set by an external feedback resistor divider carefully placed across the output , as shown in figure 3a. the regulated output voltage is determined by: v out = 0.8v 1 + r b r a ?? ? ?? ? to improve the frequency response , a feedforward ca - pacitor, c ff , may be used . great care should be taken to route the v fb line away from noise sources , such as the inductor or the sw line.for the ltc3892 and ltc3892-2, channel 1 has the option to be programmed to a fixed 5v or 3.3v output through control of the vpr g1 pin ( not available on the ltc3892-1). figure ?3b shows how the v fb1 pin is used to sense the output voltage in fixed output mode . tying vprg1 to intv cc or gnd programs v out1 to 5v or 3.3v, respectively. floating vpr g1 sets v out1 to adjustable output mode using external resistors. 38921 f05a 1/2 ltc3892/ ltc3892-1/ ltc3892-2 v fb r b c ff r a v out 38921 f05b ltc3892/ ltc3892-2 v fb1 vprg1 intv cc /gnd c out v out1 5v/3.3v figure 3. setting buck output voltage (3a) setting adjustable output voltage (3b) setting ch1 (ltc3892) to fixed 5v/3.3v voltage downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 22 38921fb for more information www.linear.com/ltc3892 applications information run pins the ltc3892/ltc3892-1/ltc3892 -2 is enabled using the ru n1 and ru n2 pins . the run pins have a rising threshold of 1. 275v with 75mv of hysteresis . pulling a run pin below 1.2v shuts down the main control loop for that channel. pulling both run pins below 0.7v disables the controllers and most internal circuits , including the drv cc and intv cc ldos . in this state , the ltc3892/ltc3892-1/ ltc3892-2 draws only 3.6a of quiescent current.releasing a run pin allows a small 150na internal current to pull up the pin to enable that controller . because of condensation or other small board leakage pulling the pin down , it is recommended the run pins be externally pulled up or driven directly by logic . each run pin can tolerate up to 65v ( absolute maximum ), so it can be conveniently tied to v in in always-on applications where one or more controllers are enabled continuously and never shut down . the run pins can be implemented as a uvlo by con - necting them to the output of an external resistor divider network off v in , as shown in figure 4. 3892 f04 1/2 ltc3892/ ltc3892-1/ ltc3892-2 run r b r a v in figure 4. using the run pins as a uvlo the rising and falling uvlo thresholds are calculated using the run pin thresholds and pull-up current: v uvlo(rising) = 1.275v 1 + r b r a ?? ? ?? ? C 150na ? r b v uvlo(falling) = 1.20v 1 + r b r a ?? ? ?? ? C 150na ? r b tracking and soft-start (track/ss1, track/ss2 pins) the start-up of each v out is controlled by the voltage on the track / ss pin ( track /s s1 for channel 1 , track /s s2 for channel 2 ). when the voltage on the track / ss pin is less than the internal 0.8v reference , the ltc3892/ ltc3892-1/ltc3892 -2 regulates the v fb pin voltage to the voltage on the track / ss pin instead of the internal reference. the track / ss pin can be used to program an external soft-start function or to allow v out to track another supply during start-up. soft-start is enabled by simply connecting a capacitor from the track / ss pin to ground , as shown in figure ?5. an internal 10 a current source charges the capacitor , providing a linear ramping voltage at the track / ss pin . the ltc3892/ltc3892-1/ltc3892 -2 will regulate its feedback voltage ( and hence v out ) according to the voltage on the track/ ss pin , allowing v out to rise smoothly from 0v to its final regulated value . the total soft-start time will be approximately: t ss = c ss ? 0.8v 10a 38921 f06 1/2 ltc3892/ ltc3892/ ltc3892-2 track/ssgnd c ss figure 5. using the track/ss pin to program soft-start downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 23 38921fb for more information www.linear.com/ltc3892 applications information alternatively, the track /ss1 and track /ss2 pins can be used to track two ( or more ) supplies during start-up , as shown qualitatively in figures 6a and 6b. to do this , a resistor divider should be connected from the master sup - ply (v x ) to the track / ss pin of the slave supply (v out ), as shown in figure 7 . during start-up v out will track v x according to the ratio set by the resistor divider: v x v out = r a r tracka ? r tracka + r trackb r a + r b for coincident tracking (v out = v x during start-up), r a = r tracka r b = r trackb figure 6. two different modes of output voltage tracking 38921 f07a v x(master) v out(slave) output (v out ) time (6a) coincident tracking 38921 f07b v x(master) v out(slave) output (v out ) time (6b) ratiometric tracking 38921 f08 1/2 ltc3892/ ltc3892-1/ ltc3892-2 v fb track/ss r b r a v out r trackb r tracka v x figure 7. using the track/ss pin for tracking drv cc and intv cc regulators and extv cc (opti-drive) the ltc3892 / ltc3892-1 / ltc3892 -2 features two separate internal p-channel low dropout linear regulators ( ldo ) that supply power at the drv cc pin from either the v in supply pin or the extv cc pin depending on the connections of the extv cc , drvset , and drvuv pins . a third p-channel ldo supplies power at the intv cc pin from the drv cc pin . drv cc powers the gate drivers whereas intv cc powers much of the ltc3892/ltc3892-1/ltc3892-2 s internal circuitry . the v in ldo and the extv cc ldo regulate drv cc between 5v to 10v, depending on how the drvset pin is set . each of these ldos can supply a peak current of at least 50ma and must be bypassed to ground with a minimum of 4 .7 f ceramic capacitor . good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels . the intv cc supply must be bypassed with a 0.1f ceramic capacitor. the drvset pin programs the drv cc supply voltage and the drvuv pin selects different drv cc uvlo and extv cc switchover threshold voltages . table 2a summarizes the different drvset pin configurations along with the volt - age settings that go with each configuration . table 2b summarizes the different drvuv pin settings . tying the downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 24 38921fb for more information www.linear.com/ltc3892 applications information drvset pin to intv cc programs drv cc to 10v. tying the drvset pin to gnd programs drv cc to 6v. by placing a 50k to 100k resistor between drvset and gnd the drv cc voltage can be programmed between 5v to 10v, as shown in figure 8. table 2a drvset pin drv cc voltage gnd 6v intv cc 10v resistor to gnd 50k to 100k 5v to 10v table 2b drvuv pin drv cc uvlo rising / falling thresholds extv cc switchover rising / falling threshold gnd 4.0v / 3.8v 4.7v / 4.45v intv cc 7.5v / 6.7v 7.7v / 7.45v ic in this case is highest and is equal to v in ? i drvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section . the junction temperature can be estimated by using the equations given in note 2 of the electrical characteristics . for example , using the ltc3892 in the qfn package , the drv cc current is limited to less than 31ma from a 40v supply when not using the extv cc supply at a 70 c ambi - ent temperature: t j = 70c + (31ma)(40v)(44c/w) = 125c to prevent the maximum junction temperature from being exceeded, the v in supply current must be checked while operating in forced continuous mode (pllin/mode = intv cc ) at maximum v in . when the voltage applied to extv cc rises above its switchover threshold , the v in ldo is turned off and the extv cc ldo is enabled . the extv cc ldo remains on as long as the voltage applied to extv cc remains above the switchover threshold minus the comparator hysteresis . the extv cc ldo attempts to regulate the drv cc voltage to the voltage as programmed by the drvset pin , so while extv cc is less than this voltage , the ldo is in dropout and the drv cc voltage is approximately equal to extv cc . when extv cc is greater than the programmed voltage , up to an absolute maximum of 14v, drv cc is regulated to the programmed voltage. using the extv cc ldo allows the mosfet driver and control power to be derived from one of the ltc3892/ ltc3892-1 / ltc3892-2 s switching regulator outputs (4.7v/7.7v v out 14v) during normal operation and from the v in ldo when the output is out of regulation (e.g., start-up, short circuit ). if more current is required through the extv cc ldo than is specified , an external schottky diode can be added between the extv cc and drv cc pins . in this case , do not apply more than 10v to the extv cc pin and make sure that extv cc v in . significant efficiency and thermal gains can be realized by powering drv cc from the output , since the v in cur - rent resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher efficiency). figure 8. relationship between drv cc voltage and resistor value at drvset pin drvset pin resistor (k) 50 4 drv cc voltage (v) 5 7 8 9 11 55 75 85 38921 f09 6 10 70 95 100 60 65 80 90 high input voltage applications in which large mosf ets are being driven at high frequencies may cause the maximum junction temperature rating for the ltc3892/ltc3892-1/ ltc3892 -2 to be exceeded . the drv cc current , which is dominated by the gate charge current , may be supplied by either the v in ldo or the extv cc ldo . when the voltage on the extv cc pin is less than its switchover threshold (4.7v or 7.7v as determined by the drvuv pin described above), the v in ldo is enabled . power dissipation for the downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 25 38921fb for more information www.linear.com/ltc3892 applications information for 5v to 14v regulator outputs , this means connecting the extv cc pin directly to v out . tying the extv cc pin to an 8.5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (31ma)(8.5v)(44c/w) = 82c however , for 3. 3v and other low voltage outputs , additional circuitry is required to derive drv cc power from the output . the following list summarizes the four possible connec - tions for extv cc : 1. extv cc grounded . this will cause drv cc to be powered from the internal v in regulator resulting in increased power dissipation in the ltc3892 / ltc3892-1 / ltc3892-2 at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5v to 14v regulator and provides the highest efficiency. 3. extv cc connected to an external supply . if an external supply is available in the 5v to 14v range , it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements . ensure that extv cc < v in . 4. extv cc connected to an output-derived boost network . for 3.3v and other low voltage regulators , efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v/7.7v. topside mosfet driver supply (c b ) external bootstrap capacitors , c b , connected to the boost pins supply the gate drive voltage for the topside mosfet. the ltc3892/ltc3892-1/ltc3892 -2 features an internal switch between drv cc and the boost pin for each controller . these internal switches eliminate the need for external bootstrap diodes between drv cc and boost. capacitor c b in the functional diagram is charged through this internal switch from drv cc when the sw pin is low . when the topside mosfet is to be turned on , the driver places the c b voltage across the gate-source of the mosfet . this enhances the top mosfet switch and turns it on . the switch node voltage , sw , rises to v in and the boost pin follows . with the topside mosfet on , the boost voltage is above the input supply : v boost = v in + v drvcc . the value of the boost capacitor , c b , needs to be 100 times that of the total input capacitance of the topside mosfet(s). fault conditions: current limit and current foldback the ltc3892/ltc3892-1 ( not the ltc3892-2) includes current foldback to help limit load current when an output is shorted to ground . if the output voltage falls below 70% of its nominal output level , then the maximum sense voltage is progressively lowered from 100 % to 40 % of its maximum selected value. under short-circuit conditions with very low duty cycles , the channel will begin cycle skipping in order to limit the short-circuit current . in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation . the short-circuit ripple current is determined by the minimum on-time , t on ( min ) , of the lt c3892 / lt c3892 -1 / lt c3892 -2 ( 80ns ), the input voltage and inductor value: ? i l(sc) = t on(min) v in l ?? ? ?? ? the resulting average short-circuit current is: i sc = 40% ? i lim(max) ? 1 2 ? i l(sc) ( ltc3892 / ltc3892-1 ) i sc = i lim(max) ? 1 2 ? i l(sc ) ( ltc3892-2) fault conditions: overvoltage protection (crowbar) (ltc3892/ltc3892-1; not on ltc3892-2) the overvoltage crowbar is designed to blow a system input fuse when the output voltage of the regulator rises much higher than nominal levels . the crowbar causes huge currents to flow , that blow the fuse to protect against a shorted top mosfet if the short occurs while the controller is operating. a comparator monitors the output for overvoltage condi - tions. the comparator detects faults greater than 10 % downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 26 38921fb for more information www.linear.com/ltc3892 applications information above the nominal output voltage . when this condition is sensed , the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. the bottom mosfet remains on continuously for as long as the overvoltage condition persists ; if v out returns to a safe level, normal operation automatically resumes. a shorted top mosfet will result in a high current condition which will open the system fuse . the switching regulator will regulate properly with a leaky top mosfet by altering the duty cycle to accommodate the leakage. fault conditions: overtemperature protection at higher temperatures , or in cases where the internal power dissipation causes excessive self heating on chip ( such as drv cc short to ground ), the overtemperature shutdown cir - cuitry will shut down the ltc 3892 / ltc3892-1 / ltc3892-2 . when the junction temperature exceeds approximately 175c, the overtemperature circuitry disables the drv cc ldo, causing the drv cc supply to collapse and effectively shutting down the entire ltc3892 / ltc3892-1 / ltc3892-2 chip. once the junction temperature drops back to the ap - proximately 155 c, the drv cc ldo turns back on . long- term overstress (t j > 125 c) should be avoided as it can degrade the performance or shorten the life of the part. phase-locked loop and frequency synchronization the ltc3892 / ltc3892-1 / ltc3892 -2 has an internal phase-locked loop (pll) comprised of a phase frequency detector, a lowpass filter , and a voltage-controlled oscilla - tor (vco). this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the pllin / mode pin . the turn-on of controller 2 s top mosfet is thus 180 out of phase with the external clock . the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators . this type of phase detector does not exhibit false lock to harmonics of the external clock. if the external clock frequency is greater than the internal oscillator s frequency , f osc , then current is sourced continu - ously from the phase detector output , pulling up the vco input . when the external clock frequency is less than f osc , current is sunk continuously , pulling down the vco input . if the external and internal frequencies are the same but exhibit a phase difference , the current sources turn on for an amount of time corresponding to the phase difference . the voltage at the vco input is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point , the phase detector output is high impedance and the internal filter capacitor , clp, holds the voltage at the vco input.note that the ltc3892/ltc3892-1/ltc3892 -2 can only be synchronized to an external clock whose frequency is within range of the ltc3892/ltc3892-1/ltc3892-2s internal vco , which is nominally 55khz to 1mhz. this is guaranteed to be between 75khz and 850khz. typically , the external clock ( on the pllin / mode pin ) input high threshold is 1.6v, while the input low threshold is 1.1v. the ltc3892/ltc3892-1/ltc3892 -2 is guaranteed to synchronize to an external clock that swings up to at least 2.5v and down to 0.5v or less. rapid phase locking can be achieved by using the freq pin to set a free-running frequency near the desired synchronization frequency . the vco s input voltage is prebiased at a frequency corresponding to the frequency set by the freq pin . once prebiased , the pll only needs to adjust the frequency slightly to achieve phase lock and synchronization. although it is not required that the free- running frequency be near the external clock frequency , doing so will prevent the operating frequency from passing through a large range of frequencies as the pll locks. freq pin resistor (k) 15 frequency (khz) 600 800 1000 35 45 55 25 38921 f10 400 200 500 700 900 300 100 0 65 75 85 95 105 115 125 figure 9. relationship between oscillator frequency and resistor value at the freq pin downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 27 38921fb for more information www.linear.com/ltc3892 applications information table 3 summarizes the different states in which the freq pin can be used . when synchronized to an external clock , the ltc3892/ltc3892-1/ltc3892 -2 operates in forced continuous mode at light loads. table 3 freq pin pllin/mode pin frequency 0v dc voltage 350khz intv cc dc voltage 535khz resistor to gnd dc voltage 50khz to 900khz any of the above external clock 75khz to 850khz phase locked to external clock minimum on-time considerations minimum on-time , t on(min) , is the smallest time duration that the ltc3892/ltc3892-1/ltc3892 -2 is capable of turning on the top mosfet . it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in (f) if the duty cycle falls below what can be accommodated by the minimum on-time , the controller will begin to skip cycles. the output voltage will continue to be regulated , but the ripple voltage and current will increase.the minimum on-time for the ltc3892 / ltc3892-1 / ltc3892 -2 is approximately 80ns. however , as the peak sense voltage decreases , the minimum on-time gradually increases up to about 130ns. this is of particular concern in forced continuous applications with low ripple current at light loads . if the duty cycle drops below the minimum on-time limit in this situation , a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100 %. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement . percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power.although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3892/ltc3892-1/ltc3892 -2 circuits : 1 ) ic v in current , 2 ) drv cc regulator current , 3 ) i 2 r losses , 4 ) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table , which excludes mosfet driver and control currents . v in current typically results in a small (<0.1%) loss. 2. drv cc current is the sum of the mosfet driver and control currents . the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again , a packet of charge , dq , moves from drv cc to ground . the resulting dq / dt is a cur - rent out of drv cc that is typically much larger than the control circuit current . in continuous mode , i gatechg = f (q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. supplying drv cc from an output-derived source power through extv cc will scale the v in current required for the driver and control circuits by a factor of ( duty cycle )/ (efficiency). for example , in a 20v to 5v application , 10ma of drv cc current results in approximately 2.5ma of v in current . this reduces the midcurrent loss from 10% or more ( if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse ( if used ), mosfet , inductor , current sense resis - tor and input and output capacitor esr . in continuous mode the average output current flows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet . if the two mosfets have approximately the same r ds(on) , then the resis - tance of one mosfet can simply be summed with the resistances of l , r sense and esr to obtain i 2 r losses . downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 28 38921fb for more information www.linear.com/ltc3892 applications information for example , if each r ds(on) = 30m, r l = 50m, r sense = 10m and r esr = 40m ( sum of both input and output capacitance losses ), then the total resistance is 130m. this results in losses ranging from 3 % to 13% as the output current increases from 1a to 5a for a 5v output , or a 4 % to 20 % loss for a 3.3v output . efficiency varies as the inverse square of v out for the same external components and output power level . the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the top mosfet (s), and become significant only when operating at high input voltages (typically 20v or greater ). transition losses can be estimated from: transition loss = (1.7) ? v in 2 ? i o(max) ? c rss ? f other hidden losses such as copper trace and internal battery resistances can account for an additional 5 % to 10 % efficiency degradation in portable systems . it is very important to include these system level losses during the design phase . the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency . a 25w supply will typically require a minimum of 20 f to 40 f of capacitance having a maximum of 20m to 50m of esr . other losses including schottky conduction losses during dead-time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response . switching regulators take several cycles to respond to a step in dc (resistive) load current . when a load step occurs , v out shifts by an amount equal to ? i load(esr) , where esr is the effective series resistance of c out . ? i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value . during this recov - ery time v out can be monitored for excessive overshoot or ringing , which would indicate a stability problem . opti-loop compensation allows the transient response to be optimized over a wide range of output capacitance and esr values . the availability of the ith pin not only allows optimization of control loop behavior , but it also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step , rise time and settling at this test point truly reflects the closed-loop response . assuming a predominantly second order system , phase margin and / or damping factor can be estimated using the percentage of overshoot seen at this pin . the bandwidth can also be estimated by examining the rise time at the pin . the ith external components shown in figure 12 circuit will provide an adequate starting point for most applications . the ith series r c -c c filter sets the dominant pole-zero loop compensation . the values can be modified slightly to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined . the output capacitors need to be selected because the various types and values determine the loop gain and phase . an output current pulse of 20 % to 80 % of full-load current having a rise time of 1 s to 10 s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet directly across the output ca - pacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop , so this signal cannot be used to determine phase margin . this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response . the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by de - creasing c c . if r c is increased by the same factor that c c is decreased , the zero frequency will be kept the same , thereby keeping the phase shift the same in the most critical frequency range of the feedback loop . the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 29 38921fb for more information www.linear.com/ltc3892 applications information a second , more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors . the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly . if the ratio of c load to c out is greater than 1 :50, the switch rise-time should be controlled so that the load rise-time is limited to approximately 25 ? c load . thus a 10 f capacitor would require a 250 s rise time , limiting the charging current to about 200ma.design example as a design example for one channel , assume v in = 12v (nominal), v in = 22v (maximum), v out = 3.3v, i max = 5a, v sense(max) = 75mv and f = 350khz. the inductance value is chosen first based on a 30 % ripple current as - sumption. the highest value of ripple current occurs at the maximum input voltage . tie the freq pin to gnd , generating 350khz operation . the minimum inductance for 30% ripple current is: ? i l = v out f ( ) l ( ) 1 ? v out v in(nom) ?? ? ?? ? a 4 .7 h inductor will produce 29 % ripple current . the peak inductor current will be the maximum dc value plus one half the ripple current , or 5.73a. increasing the ripple current will also help ensure that the minimum on-time of 80ns is not violated . the minimum on-time occurs at maximum v in : t on(min) = v out v in(max) f ( ) = 3.3v 22v 350khz ( ) = 429ns the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (66mv): r sense 66mv 5.73a 0.01 ? choosing 1 % resistors : r a = 25k and r b = 78.7k yields an output voltage of 3.32v. the power dissipation on the topside mosfet can be easily estimated. choosing a fairchild fd s6982 s dual mosfet results in : r ds(on) = 0.035/0.022, c miller = 215pf. at maximum input voltage with t(estimated) = 50c: p main = 3.3v 22v 5a ( ) 2 1 + 0.005 ( ) 50 c ? 25 c ( ) ?? ?? 0.035 ? ( ) + 22v ( ) 2 5a 2 2.5 ? ( ) 215pf ( ) ? 1 6v ? 2.3v + 1 2.3v ?? ? ?? ? 350khz ( ) = 308mw a short-circuit to ground will result in a folded back current of : i sc = 34mv 0.01 ? ? 1 2 80ns 22v ( ) 4.7h ?? ? ?? ? = 3.21a with a typical value of r ds ( on ) and = (0. 005 / c )( 25 c) = 0 . 125 . the resulting power dissipated in the bottom mosfet is: p sync = (3.21a) 2 (1.125) (0.022) = 255mw which is less than under full-load conditions. c in is chosen for an rms current rating of at least 3a at temperature assuming only this channel is on . c out is chosen with an esr of 0.02 for low output ripple . the output ripple in continuous mode will be highest at the maximum input voltage . the output voltage ripple due to esr is approximately: v o(ripple) = r esr ( ? i l ) = 0.02 (1.45a) = 29mv p-p pc board layout checklist when laying out the printed circuit board , the following checklist should be used to ensure proper operation of the ic. figure 10 illustrates the current waveforms present in the various branches of the 2- phase synchronous buck regulators operating in the continuous mode . check the following in your layout:1. are the top n-channel mosfets mto p1 and mto p2 located within 1cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 30 38921fb for more information www.linear.com/ltc3892 applications information 2. are the signal and power grounds kept separate ? the combined ic signal ground pin and the ground return of c drvcc must return to the combined c out (C) termi - nals. the path formed by the top n-channel mosfet , schottky diode and the c in capacitor should have short leads and pc trace lengths . the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. does the ltc3892/ltc3892-1/ltc3892 -2 v fb pin s resistive divider connect to the (+) terminal of c out ? the resistive divider must be connected between the (+) terminal of c out and signal ground . the feedback resistor connections should not be along the high cur - rent input feeds from the input capacitor(s). 4. are the sense C and sense + leads routed together with minimum pc trace spacing ? the filter capacitor between sense + and sense C should be as close as possible to the ic . ensure accurate current sensing with kelvin connections at the sense resistor. 5. is the drv cc and decoupling capacitor connected close to the ic , between the drv cc and the ground pin ? this capacitor carries the mosfet drivers current peaks. 6. keep the switching nodes (sw1, sw2 ), top gate (tg1, tg2), and boost nodes (boost1, boost2 ) away from sensitive small-signal nodes , especially from the op - r l1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l2 bold lines indicatehigh switching current. keep lines to a minimum length. l2 sw2 38921 f11 r sense2 v out2 c out2 figure 10. branch current waveforms downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 31 38921fb for more information www.linear.com/ltc3892 applications information posites channel s voltage and current sensing feedback pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the ltc3892/ltc3892-1/ltc3892 -2 and occupy minimum pc trace area. 7. use a modified star ground technique : a low impedance , large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the drv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the gnd pin of the ic. pc board layout debuggingstart with one controller at a time . it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit . monitor the output switching node ( sw pin ) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well . check for proper performance over the operating voltage and current range expected in the application . the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold typi - cally 25 % of the maximum designed current level in burst mode operation . t he duty cycle percentage should be maintained from cycle to cycle in a well-designed , low noise pcb implementation . variation in the duty cycle at a subharmonic rate can sug - gest noise pickup at the current or voltage sensing inputs or inadequate loop compensation . overcompensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required . only after each controller is checked for its individual performance should both should multiple controllers be turned on at the same time. a particularly difficult region of operation is when one channel is nearing its current comparator trip point when the other channel is turning on its top mosfet . this occurs around 50 % duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout . check the operation of the un - dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation.investigate whether any problems exist only at higher out - put currents or only at higher input voltages . if problems coincide with high input voltages and low output currents , look for capacitive coupling between the boost , sw , tg , and possibly bg connections and the sensitive voltage and current pins . the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic . this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling . if problems are encountered with high current output loading at lower input voltages , look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces . in addition , investigate common ground path voltage pickup between these components and the gnd pin of the ic. an embarrassing problem , which can be missed in an otherwise properly working switching regulator , results when the current sensing leads are hooked up backwards . the output voltage under this improper hookup will still be maintained but the advantages of current mode control will not be realized . compensation of the voltage loop will be much more sensitive to component selection . this behavior can be investigated by temporarily shorting out the current sensing resistor don t worry , the regulator will still maintain control of the output voltage. downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 32 38921fb for more information www.linear.com/ltc3892 typical applications c drvcc 4.7f mbot2 mtop2 c b2 0.1f l2 15h 8m r sns2 c ith2b 100pf r a2 100k r b2 7.15k c out2b 10f r ith2 34.8k c ith2a 1nf c out2a 150f c sns2 1nf c ss2 0.1f c intvcc 0.1f mbot1 mtop1 c b1 0.1f l1 5.6h 5m r sns1 c ith1b 100pf c out1b 10f r ith1 7.5k c ith1a 2.2nf c out1a 220f c sns1 1nf c ss1 0.1f r pg1 1000k r pg2 1000k c inb 2.2fx5 c ina 47f r freq 35.7k ltc3892 vin run2 intv cc pllin/mode gnd freq sw2 bg2 tg2 boost2 sense2 + v fb2 ith2 track/ss2 12v* sense2 C drvuv extv cc pgood2 drv cc run1 sw1 bg1 tg1 boost1 sense1 + v fb1 ith1 track/ss1 sense1 C drvset vprg1 pgood1 v out2 v out2 5a 5v v out1 8a vin top1, top2: bsc057n08ns3 8v to 60v bot1, bot2: bsc036ne7ns3 l1: coilcraft xal1010-562me l2: coilcraft xal1010-153me ilim 3892 ta02 *v out2 follows v in when v in 12v figure 11. high efficiency dual 5v/12v step-down converter with 10v gate drive load current (a) 0.0001 0.001 0.01 0.1 1 10 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1k 10k efficiency (%) power loss (mw) vs load current ef?ciency and power loss 3892 ta02b efficiency v in = 12v v out = 5v power loss downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 33 38921fb for more information www.linear.com/ltc3892 typical applications figure 12. high efficiency dual 3.3v/8.5v step-down converter with 6v gate drive c drvcc 4.7f mbot2 mtop2 c b2 0.1f l2 8.0h 10m r sns2 c ith2b opt r a2 100k r b2 10.5k c out2b 10f r ith2 34.8k c ith2a 470pf c out2a 330f c sns2 1nf c ss2 0.01f c intvcc 0.1f mbot1 mtop1 c b1 0.1f l1 4.7h 8m r sns1 c ith1b 100pf c out1b 10f r ith1 20k c ith1a 1nf c out1a 470f c sns1 1nf c ss1 0.01f r pg1 100k r pg2 100k c inb 2.2f c ina 100f r freq 41.2k ltc3892 vin run2 intv cc pllin/mode gnd freq sw2 bg2 tg2 boost2 sense2 + v fb2 ith2 track/ss2 sense2 C drvuv extv cc pgood2 drv cc run1 sw1 bg1 tg1 boost1 sense1 + v fb1 ith1 track/ss1 sense1 C drvset vprg1 pgood1 v out2 v out2 8.5v*3a 3.3v v out1 5a v in top1, top2, bot1, bot2: rjk0651dpb 4.5v to 60v l1: coilcraft ser1360-472kl l2: coilcraft ser1360-802kl x3 c out2a : sanyo 10tpe330m c out1a : sanyo 6tpe470m ilim 3892 ta03 *v out2 follows v in when v in 8.5v load current (a) 0.0001 0.001 0.01 0.1 1 10 0 10 20 30 40 50 60 70 80 90 100 0.1 1 10 100 1k 10k efficiency (%) power loss (mw) vs load current ef?ciency and power loss 3892 ta03b v in = 12v v out = 3.3v efficiency power loss downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 34 38921fb for more information www.linear.com/ltc3892 typical applications figure 13. high efficiency dual-phase step-down 5v/8.5v converter with 8v gate drive c drvcc 4.7f mbot2 mtop2 c b2 0.1f l2 6.5h 15m r sns2 c ith2b 68pf r a2 649k r b2 68.1k c4.7f out2b r ith2 15kk c ith2a 2.2nf c out2a 68f c sns2 1nf c ss2 0.1f c intvcc 0.1f mbot1 mtop1 c b1 0.1f l1 4.9h 9m r sns1 c ith1b 100pf c out1b 22f r ith1 15k c ith1a 1.5nf c out1a 220f c sns1 1nf c ss1 0.1f c inb 2.2fx3 c ina 33f r80.6k drvcc r a1 357k r b1 68.1k ltc3892 -1 vin run2 intv cc pllin/mode gnd sw2 bg2 tg2 boost2 sense2 + v fb2 ith2 track/ss2 sense2 C drvuv extv cc drv cc run1 sw1 bg1 tg1 boost1 sense1 + v fb1 ith1 track/ss1 sense1 C drvset v out2 v out2 8.5v*3a v out1 5v5a vin 4.5v to 60v top1, top2, bot1, bot2: bsz123n08ns3 l1: wurth 744314490 l2: wurth 744314490 c out2a : sanyo 10tpc68m c out1a : sanyo 6tpb220ml freq 3892 ta05 *v out2 follows v in when v in 8.5v downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 35 38921fb for more information www.linear.com/ltc3892 package description please refer to http:// www .linear.com/product/ltc3892#packaging for the most recent package drawings. fe28 (ea) tssop rev k 0913 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 19 20 22 21 15 16 18 17 9.60 C 9.80* (.378 C .386) 7.56 (.298) 3.05 (.120) 28 2726 25 24 23 1.20 (.047) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 0.195 C 0.30 (.0077 C .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 7.56 (.298) 3.05 (.120) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note:1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev k) exposed pad variation ea downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 36 38921fb for more information www.linear.com/ltc3892 package description please refer to http:// www .linear.com/product/ltc3892#packaging for the most recent package drawings. 5.00 0.10 (4 sides) note:1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1top mark (note 6) 0.40 0.10 31 12 32 bottom viewexposed pad 3.50 ref (4-sides) 3.45 0.10 3.45 0.10 0.75 0.05 r = 0.115 typ 0.25 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 C 0.05 0.70 0.05 3.50 ref (4 sides) 4.10 0.05 5.50 0.05 0.25 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.45 0.05 3.45 0.05 uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 37 38921fb for more information www.linear.com/ltc3892 information furnished by linear technology corporation is believed to be accurate and reliable . however, no responsibility is assumed for its use . linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights . revision history rev date description page number a 12/15 add ltc3892-2 version 1 to 38 b 05/16 modified graph, oscillator frequency vs temperature 10 downloaded from: http:///
lt c3892/ lt c3892 -1 / lt c3892 -2 38 38921fb for more information www.linear.com/ltc3892 ? linear technology corporation 2015 lt 0516 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3892 related parts typical application part number description comments ltc3890/ltc3890-1 ltc3890-2/ltc3890-3 60v, low i q , dual 2-phase synchronous step-down dc/dc controller with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v??v out ??24v, i q = 50a ltc3891 60v, low i q , synchronous step-down dc/dc controller with 99% duty cycle pll fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v??v out ??24v, i q = 50a ltc3864 60v, low i q , high voltage dc/dc controller with 100% duty cycle fixed frequency 50khz to 850khz, 3.5v v in 60v, 0.8v??v out ??v in , i q = 40a, msop-12e, 3mm 4mm dfn-12 ltc3899 60v, triple output, buck/buck/boost synchronous controller with 29a burst mode i q 4.5v (down to 2.2v after start-up) v in 60v, v out up to 60v, buck v out range: 0.8v to 60v, boost v out up to 60v ltc3859al 38v, low i q , triple output , buck /buck/ boost synchronous controller with 28a burst mode i q 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, buck v out range: 0.8v to 24v, boost v out up to 60v, ltc3857/ltc3857-1 ltc3858/ltc3858-1 38v, low i q , dual output 2-phase synchronous step-down dc/dc controller with 99% duty cycle pll fixed operating frequency 50khz to 900khz, 4v v in 38v, 0.8v v out 24v, i q = 50a/170a ltc3807 38v, low i q , synchronous step-down controller with 24v output voltage capability pll fixed frequency 50khz to 900khz, 4v v in 38v, 0.8v??v out ??24v, i q = 50a c drvcc 4.7f mbot2 mtop2 c b2 0.1f l2 10h 3m r sns2 c out2b 10f c out2a 150f c sns2 1nf c intvcc 0.1f mbot1 mtop1 c b1 0.1f l1 10h 3m r sns1 c ith1b 47pf c out1b 10f r ith1 9.78k c ith1a 4.7nf c out1a 150f c sns1 1nf c ss1 0.1f c inb 2.2f c ina 100f r freq 29.4k r a1 100k r b1 7.15k c ith2a 47pf ltc3892 -1 vin run2 intv cc pllin/mode gnd freq sw2 bg2 tg2 boost2 sense2 + v fb2 ith2 track/ss2 12v sense2 C drvuv extv cc drv cc run1 sw1 bg1 tg1 boost1 sense1 + v fb1 ith1 track/ss1 sense1 C drvset vout vout 30a vin top1, top2: bsc123n08ns3g 16v to 60v bot1, bot2: bsc047n08ns3g l1, l2: coilcraft ser2918h-103kl x5 x2 x2 x2 x2 3892 ta04 figure 14. high current dual-phase single output step-down 12v converter downloaded from: http:///

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